In many modern electronics applications, it is desirable to convert an analog signal to a digital value. For example, in a radio frequency (RF) transceiver, a received analog RF signal may be demodulated to an analog baseband signal which is then converted to a digital baseband signal for subsequent digital signal processing. Many electrical systems utilize analog-to-digital converters (ADCs) to convert an analog signal to a digital value. However, because of the finite nature of digital representation, quantization error (which is the difference between the actual analog value and quantized digital value due to rounding or truncation) is an imperfection inherent to the analog-to-digital conversion. In some ADCs, sigma-delta modulation (or alternatively, delta-sigma modulation) is used to reduce the effect of quantization error and improve signal-to-noise ratio (SNR). Sigma-delta modulation (alternatively referred to as delta-sigma modulation) adds or subtracts quantization error to a forward signal path using feedback loops and integrator circuits. The quantization error is oversampled at a frequency greater than the analog input signal frequency, thereby allowing it to be filtered at the integrators without noticeably impacting the signal.
Many systems utilize continuous-time sigma-delta modulators, that is, sigma-delta modulators constructed using continuous-time circuitry. Continuous-time sigma-delta modulators can be clocked at higher sampling frequencies which improves the performance of the sigma-delta modulator. In practice, however, high-speed sigma-delta modulators (generally sigma-delta modulators with sampling frequencies in the MHz range or higher) suffer from various circuit level effects which can lead to instability and degrade performance (e.g., SNR) of the modulator. Many modulators exhibit delay, referred to as excess loop delay, that results from, for example, the nonzero switching time of transistors and/or comparators utilized in the quantizer and/or digital-to-analog converters (DACs) in the feedback loop. In addition, at higher speeds, clock jitter and/or intersymbol interference (ISI) begin to distort the waveforms of the feedback signals. While these problems may be reduced with improvements to the hardware and/or electrical components, in general, these improvements entail prohibitive increases in cost, area, and power consumption.
Some prior art systems utilize finite impulse response (FIR) filters in single-bit ADCs to filter each feedback signal (i.e., the number of FIR filters is equal to the number of integrators) in the feedback loop to reduce the modulator's sensitivity to clock jitter. However, in practical implementations, the loop delay creates instability, which requires these systems to be realized with either return-to-zero (RZ) DACs or by deteriorating the noise shaping capability of the modulator by reducing the out-of-band gain of the noise transfer function for the system. Using RZ DACs is undesirable because it increases the slew rate requirements for the integrators and/or other components of the modulator, which in turn increases the area and/or power consumption of the modulator. Reducing the out-of-band gain of the noise transfer function for the system is undesirable, as it degrades the SNR for the modulator. In addition, to adapt these prior art systems for multi-bit operation with adequate linearity, the feedback path must often be modified to include mismatch shaping components to account for component mismatch between the additional DACs included in the feedback path. These mismatch shaping components further exacerbate the loop delay and the resulting instability of the modulator.
Some other prior art systems attempt to mitigate the effects of loop delay by purposely inserting a constant delay in the feedback path of the sigma-delta modulator and compensating for the constant delay with an additional term in the modulator transfer function. In some prior art systems, this results in an increased voltage swing at the input of the quantizer. To offset this voltage swing, the overall gain of the modulator must be reduced, thereby reducing SNR. In addition, this approach creates a summing junction at the input of the quantizer. In order to process the high frequency signals present at the summing junction, the summing junction is often realized using an analog summer (e.g., a high-speed summing amplifier) which increases the power and area requirements for the modulator. In some prior art systems, the additional feedback path is moved from the input of the quantizer to the input of the integrator that precedes the quantizer. This increases the slew rate at the input of the integrator, resulting in an integrator that consumes additional power and area, which offsets and power and/or area savings from eliminating the analog summer. Other systems utilize proportional-integral (PI) compensation or other techniques which degrade the frequency response of the integrator and may lead to out-of-band peaking and other undesirable effects. However, these prior art systems fail to address the modulator's sensitivity to clock jitter, ISI, and other circuit level effects.